design_field_updates.tcl
1###############################################################################
2# This script provides the setup information for a Tandem with Field Updates
3# design. This script is sourced at the beginning of all synthesis,
4# implementation, and bitstream generation scripts to obtain information about the design structure.
5###############################################################################
6
7# Setup the desired script and output directories
8# These paths need to be updated to match your environment
9set projDir "."
10set scriptDir $projDir/field_update_scripts
11set synthDir $projDir/Synth
12set implDir $projDir/Implement
13set bitDir $projDir/Bitstreams
14set runSummary $projDir/run_summary.log
15set tclFiles [list $projDir/../../include.tcl]
16
17# Add additional update versions as required by your application.
18# NOTE: If known, the most complex update version of your design should be
19# Update1. This will improve the timing results for subsequent updates
20# versions. If your update versions are not defined ahead of time this can
21# be ignored. The most complex update version can be different than the version loaded into flash.
22set updateVer1Name ver1
23# Additional updates should be added as needed.
24set updateVer2Name ver2
25
26# PCIe Example design information. This should be updated to match
27# your design.
28set part xcku115-flvb2104-2-e
29set projName xdma_0_ex
30set ipName xdma_0
31set topModuleName xilinx_dma_pcie_ep
32set updateTopFile ./imports/xdma_app.v
33set updateModuleName xdma_app
34set updateInstName xdma_app_i
35
36
37# Identify which steps should be run when this script is executed. If
38# desired all of the steps can be disabled and run individually once
39# this file has been sourced into vivado. Additional updates versions
40# should be added as required by your application. The commands and
41# scripts for the corresponding steps must be replicated as desired.
42# Steps for the static portion of the design
43set runStaticSynth 1
44# Steps for the update version 1 portion of the design dependent on having completed runSynthStatic.
45set runUpdateVer1Synth 1
46set runUpdateVer1Impl 1
47set runUpdateVer1Bitstreams 1
48# Steps for the update version 2 portion of the design dependent on having completed runImplUpdateVer1.
49set runUpdateVer2Synth 1
50set runUpdateVer2Impl 1
51set runUpdateVer2Bitstreams 1
52# Steps for PR Verify across all Update versions
53set runPrVerify 1
54
55# Create a results file
56file delete -force $runSummary
57set fp [open $runSummary w]
58puts $fp "Run Summary for a Tandem with Field Updates design started at: [clock format [clock seconds]]"
59close $fp
60# Source the script containing the supporting procedures for write_bitstream
61source $scriptDir/generate_bitstreams.tcl
62# Source any required .tcl files if they exist
63foreach tclFile $tclFiles {
64 if {[file exists $tclFile]} {
65 source $tclFile
66 }
67}
68
69# -----------------------------------------------------------------------------
70# Process steps for the static portion of the design. This includes everything not included in the update region.
71# -----------------------------------------------------------------------------
72# Source the script to run synthesis on the static portion of the design.
73set staticSynthResult {0 0 0}
74if {$runStaticSynth} { set staticSynthResult [source $scriptDir/static_synth.tcl] }
75
76
77# -----------------------------------------------------------------------------
78# Process steps for the update version 1 portion of the design. This uses the
79# post synthesis .dcp created by the runSynthStatic step.
80# NOTE: This should be the most complex version of the update region and this
81# implementation step must be run prior to all other implementation runs.
82# This will be create placed, routed, and static logic LOC'ed .dcp files. The
83# static LOC'ed .dcp file will be used to implement subsequent updates versions.
84# -----------------------------------------------------------------------------
85# Source the script to run synthesis this update version of the design.
86set updateVer1SynthResult {0 0 0}
87if {$runUpdateVer1Synth} { set updateVer1SynthResult [source $scriptDir/update_ver1_synth.tcl] }
88
89# Source the script to run implementation with static and this update version.
90set updateVer1ImplResult {0 0 0}
91if {$runUpdateVer1Impl} { set updateVer1ImplResult [source $scriptDir/update_ver1_impl.tcl] }
92
93# Generate bitstreams for this version of the update.
94set updateVer1BitstreamsResult {0 0 0}
95if {$runUpdateVer1Bitstreams} {
96 puts "# HD INFO: Running bitstream generation on $updateVer1Name."
97 # Generate bitstreams for update version 1. This procedure takes in two arguments,
98 # the update name and the desired bitfiles that should be generated. Valid setting
99 # for the generated bitfiles field are one or more of the following TandemPCIe,
100 # TandemPROM, and/or PR. It is. Either of the Tandem options should be used to
101 # generate the bitfiles that will be loaded into the on-board flash. for US devices
102 # there is a one-to-one relationship between stage1 and stage2 files. You cannot
103 # mix and match stage2 files. A stage2 file must only be loaded into the device once
104 # following the stage1 programming. PR files cannot be loaded until stage1 and stage2
105 # files have been loaded. Updates should only be done using PR files.
106 set updateVer1BitstreamsResult [genBitForTandemFieldUpdate $updateVer1Name {TandemPCIe TandemPROM PR}]
107}
108
109
110# -----------------------------------------------------------------------------
111# Process steps for the update version 2 portion of the design. This used they
112# routed and LOC'ed .dcp created by the runImplUpdateVer1 step.
113# -----------------------------------------------------------------------------
114# Source the script to run synthesis this update version of the design.
115set updateVer2SynthResult {0 0 0}
116if {$runUpdateVer2Synth} { set updateVer2SynthResult [source $scriptDir/update_ver2_synth.tcl] }
117
118# Source the script to run implementation with static and this update version.
119set updateVer2ImplResult {0 0 0}
120if {$runUpdateVer2Impl} { set updateVer2ImplResult [source $scriptDir/update_ver2_impl.tcl] }
121
122# Generate bitstreams for this version of the update.
123set updateVer2BitstreamsResult {0 0 0}
124if {$runUpdateVer2Bitstreams} {
125 puts "# HD INFO: Running bitstream generation on $updateVer2Name."
126 # Generate bitstreams for update version 1. This procedure takes in two arguments,
127 # the update name and the desired bitfiles that should be generated. Valid setting
128 # for the generated bitfiles field are one or more of the following TandemPCIe,
129 # TandemPROM, and/or PR. It is. Either of the Tandem options should be used to
130 # generate the bitfiles that will be loaded into the on-board flash. for US devices
131 # there is a one-to-one relationship between stage1 and stage2 files. You cannot
132 # mix and match stage2 files. A stage2 file must only be loaded into the device once
133 # following the stage1 programming. PR files cannot be loaded until stage1 and stage2
134 # files have been loaded. Updates should only be done using PR files.
135 set updateVer2BitstreamsResult [genBitForTandemFieldUpdate $updateVer2Name {PR}]
136}
137
138
139# -------------------------------------------------------------------------
140# Add run steps for subsequent update versions as desired here. This should
141# be accomplished by doing the following:
142# - Replicating the updateVer2* variables in this file for updateVer3*
143# - Replicating and updating the process steps from the update version 2 section for update version 3
144# - Replicate and update the update_ver2_synth.tcl and update_ver2_impl.tcl files for update version 3
145# - Add the new update to the update_checkpoints list in the PrVerify section below
146# - Replicate and update the error reporting commands in the error reporting section of this file.
147# These steps should be repeated to create additional update versions as
148# desired.
149# -------------------------------------------------------------------------
150
151
152# -----------------------------------------------------------------------------
153# Process steps for the PR Verify operation. This used the placed and routed
154# .dcp files created from all prior implementation setps.
155# -----------------------------------------------------------------------------
156# The update_checkpoints list should include checkpoints for each update that
157# was created beyond update1. This must be updated if additional update versions have been added.
158set update_checkpoints [list \
159 $implDir/$updateVer2Name/${topModuleName}_route_design.dcp \
160]
161# Run the PR Verify operation and generate bitstreams for each implementation.
162set prVerifyResult {0 0 0}
163if {$runPrVerify } {
164 puts "# HD INFO: Running compatibility check between checkpoints."
165 # Verify that the update versions of the design are compatible with each other.
166 pr_verify -initial $implDir/$updateVer1Name/${topModuleName}_route_design.dcp -additional $update_checkpoints
167 # Error and Message Reporting
168 set warningCount [get_msg_config -severity {Warning} -count]
169 set criticalCount [get_msg_config -severity {Critical Warning} -count]
170 set errorCount [get_msg_config -severity {Error} -count]
171 puts "# HD INFO: PR Verify completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
172 set fp [open $runSummary a]
173 puts $fp "PR Verify completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
174 close $fp
175 set prVerifyResult "$errorCount $criticalCount $warningCount"
176}
177
178
179# -------------------------------------------------------------------------
180# Error reporting steps. Add additional error reporting for subsequent
181# update versions here as desired. This should be accomplished by replicating the commands below as needed.
182# -------------------------------------------------------------------------
183set errorFlag false
184
185# Static Error Reporting
186if {[lindex $staticSynthResult 0] != 0 || [lindex $staticSynthResult 1] != 0} {
187 set errorFlag true
188 puts "HD ERROR: Synthesis for Static had [lindex $staticSynthResult 0] Errors and [lindex $staticSynthResult 1] Critical Warnings."
189}
190
191# Update version 1 error reporting
192if {[lindex $updateVer1SynthResult 0] != 0 || [lindex $updateVer1SynthResult 1] != 0} {
193 set errorFlag true
194 puts "HD ERROR: Synthesis for $updateVer1Name had [lindex $updateVer1SynthResult 0] Errors and [lindex $updateVer1SynthResult 1] Critical Warnings."
195}
196if {[lindex $updateVer1ImplResult 0] != 0 || [lindex $updateVer1ImplResult 1] != 0} {
197 set errorFlag true
198 puts "HD ERROR: Implementation for $updateVer1Name had [lindex $updateVer1ImplResult 0] Errors and [lindex $updateVer1ImplResult 1] Critical Warnings."
199}
200if {[lindex $updateVer1BitstreamsResult 0] != 0 || [lindex $updateVer1BitstreamsResult 1] != 0} {
201 set errorFlag true
202 puts "HD ERROR: Bitstream generation for $updateVer1Name had [lindex $updateVer1BitstreamsResult 0] Errors and [lindex $updateVer1BitstreamsResult 1] Critical Warnings."
203}
204
205# Update version 2 error reporting
206if {[lindex $updateVer2SynthResult 0] != 0 || [lindex $updateVer2SynthResult 1] != 0} {
207 set errorFlag true
208 puts "HD ERROR: Synthesis for $updateVer2Name had [lindex $updateVer2SynthResult 0] Errors and [lindex $updateVer2SynthResult 1] Critical Warnings."
209}
210if {[lindex $updateVer2ImplResult 0] != 0 || [lindex $updateVer2ImplResult 1] != 0} {
211 set errorFlag true
212 puts "HD ERROR: Implementation for $updateVer2Name had [lindex $updateVer2ImplResult 0] Errors and [lindex $updateVer2ImplResult 1] Critical Warnings."
213}
214if {[lindex $updateVer2BitstreamsResult 0] != 0 || [lindex $updateVer2BitstreamsResult 1] != 0} {
215 set errorFlag true
216 puts "HD ERROR: Bitstream generation for $updateVer2Name had [lindex $updateVer2BitstreamsResult 0] Errors and [lindex $updateVer2BitstreamsResult 1] Critical Warnings."
217}
218
219# PR Verify Error Reporting
220if {[lindex $prVerifyResult 0] != 0 || [lindex $prVerifyResult 1] != 0} {
221 set errorFlag true
222 puts "HD ERROR: PR Verify had [lindex $prVerifyResult 0] Errors and [lindex $prVerifyResult 1] Critical Warnings."
223}
224
225# Generate a tcl Error as needed
226if { $errorFlag } {
227 return "ERROR: Design Run had Errors or Critical Warnings."
228} else {
229 return PASS
230}
generate_bitstreams.tcl
1
2# Setup of additional variables
3
4###############################################################################
5# This script defines the procedure genBitForTandemFieldUpdate which should be
6# used to generate bitstreams for Tandem with Field Updates designs.
7###############################################################################
8
9# Generate bitstreams for a Tandem with Field Updates Design. The inputs to this
10# procedure is the update name and the desired bitfiles to generate. Valid
11# options for the desired bitfiles include one or more of the following:
12# TandemPCIe, TandemPROM, and PR.
13proc genBitForTandemFieldUpdate { updateName bitstreamTypes } {
14
15 # Set the required variables
16 upvar 1 bitDir bitDir
17 upvar 1 implDir implDir
18 upvar 1 topModuleName topModuleName
19 upvar 1 runSummary runSummary
20 upvar 1 updateInstName updateInstName
21 upvar 1 tclFiles tclFiles
22 set outputPrefix $bitDir/$updateName/$updateName
23 # Create the output directory and remove previously generated files.
24 file mkdir $bitDir
25 file delete -force $bitDir/$updateName
26 file mkdir $bitDir/$updateName
27
28 puts "# HD INFO: Running bitstream generation for $updateName."
29
30 # Open the checkpoint for the initial configuration
31 open_checkpoint $implDir/$updateName/${topModuleName}_route_design.dcp
32
33 # Source any required .tcl files if they exist
34 foreach tclFile $tclFiles {
35 if {[file exists $tclFile]} {
36 source $tclFile
37 }
38 }
39
40 # Any constraints specific to bitstream generation can be added here or
41 # in the user created .xdc files.
42 # This may include but not be limited to the following constraints.
43 # set_property CONFIG_VOLTAGE <I/O voltage on the config bank> [current_design]
44 # set_property CFGBVS <GND | VCC> [current_design]
45 # set_property CONFIG_MODE <BPI16 | SPIx4> [current_design]
46
47 ###############################################################################
48 # Flash Programming Example Settings: Uncomment or modify as required by your
49 # design.
50 ###############################################################################
51 # SPI Flash Programming
52 set_property CONFIG_MODE SPIx4 [current_design]
53 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
54 set_property BITSTREAM.CONFIG.CONFIGRATE 9 [current_design]
55 set_property CFGBVS GND [current_design]
56 set_property CONFIG_VOLTAGE 1.8 [current_design]
57
58 # BPI Flash Programming
59 #set_property CONFIG_MODE BPI16 [current_design]
60 #set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
61 #set_property BITSTREAM.CONFIG.CONFIGRATE 9 [current_design]
62 #set_property CFGBVS <GND | VCC> [current_design]
63 #set_property CONFIG_VOLTAGE <voltage> [current_design]
64
65
66 # Generate Tandem PCIe Bitstreams
67 if { [lsearch -exact $bitstreamTypes "TandemPCIe"] >= 0 } {
68 set_property HD.OVERRIDE_PERSIST False [current_design]
69 set_property HD.TANDEM_BITSTREAMS Separate [current_design]
70 write_bitstream -force -bin_file -file ${outputPrefix}_tpcie > ${outputPrefix}_tpcie_write_bitstream.log
71 # Generate Flash Files Example. This must be updated to match your board and flash settings.
72 ###############################################################################
73 # Flash Programming Example Settings: Modify as required by your design.
74 ###############################################################################
75 write_cfgmem -force -format mcs -interface spix4 -size 256 -loadbit "up 0x0 ${outputPrefix}_tpcie_tandem1.bit" ${outputPrefix}_tpcie_tandem1.mcs
76 }
77
78 # Generate a Tandem PROM Bitstream
79 if { [lsearch -exact $bitstreamTypes "TandemPROM"] >= 0 } {
80 set_property HD.OVERRIDE_PERSIST False [current_design]
81 set_property HD.TANDEM_BITSTREAMS Combined [current_design]
82 write_bitstream -force -bin_file -file ${outputPrefix}_tprom > ${outputPrefix}_tprom_write_bitstream.log
83 # Generate Flash Files Example. This must be updated to match your board and flash settings.
84 ###############################################################################
85 # Flash Programming Example Settings: Modify as required by your design.
86 ###############################################################################
87 write_cfgmem -force -format mcs -interface spix4 -size 256 -loadbit "up 0x0 ${outputPrefix}_tpcie_tandem1.bit" ${outputPrefix}_tpcie_tandem1.mcs
88 }
89
90 # Generate update region PR Only Bitstreams
91 if { [lsearch -exact $bitstreamTypes "PR"] >= 0 && [lsearch -exact $bitstreamTypes "TandemPCIe"] < 0 && [lsearch -exact $bitstreamTypes "TandemPROM"] < 0 } {
92 set_property HD.OVERRIDE_PERSIST False [current_design]
93 set_property HD.TANDEM_BITSTREAMS None [current_design]
94 write_bitstream -force -cell [get_cells $updateInstName] -bin_file -file ${outputPrefix}_update_region_partial > ${outputPrefix}_update_region_partial_write_bitstream.log
95 }
96
97 # Error and Message Reporting
98 set warningCount [get_msg_config -severity {Warning} -count]
99 set criticalCount [get_msg_config -severity {Critical Warning} -count]
100 set errorCount [get_msg_config -severity {Error} -count]
101 puts "# HD INFO: Bitstream generation for $updateName completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
102 set fp [open $runSummary a]
103 puts $fp "Bitstream generation for $updateName completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
104 close $fp
105
106 close_project
107 return "$errorCount $criticalCount $warningCount"
108}
static_synth.tcl
1
2# Setup of additional variables
3
4###############################################################################
5# This script demonstrates how to synthesize the static portion of the example
6# design for a Tandem with Field Updates design.
7###############################################################################
8
9# Create the output directory and delete the previously generated files.
10file mkdir $synthDir
11file delete -force $synthDir/$topModuleName
12file mkdir $synthDir/$topModuleName
13
14puts "# HD INFO: Generating a blackbox module for $updateModuleName"
15
16# Generate a blackbox module for the update module by performing a search and
17# replace on the update top module file. This inserts "(* black_box *)" before the module declaration.
18set updateTopBlackboxFile "$synthDir/$topModuleName/[file rootname [file tail $updateTopFile]]_blackbox.v"
19set inFile [open $updateTopFile r]
20set outFile [open $updateTopBlackboxFile w]
21while {[gets $inFile lineIn] != -1} {
22 # Match a string "<whitespace>module<whitespace>moduleName>"
23 [regsub -line [subst -nocommands {^[ \t]*module[ \t]*${updateModuleName}}] $lineIn [subst -nocommands {(* black_box *) module ${updateModuleName}}] lineOut]
24 puts $outFile $lineOut
25}
26close $inFile
27close $outFile
28
29puts "# HD INFO: Running synthesis for module $topModuleName"
30
31# Create a project and add the required static synthesis files.
32create_project -in_memory -part $part
33set_property BOARD_PART xilinx.com:kcu1500:part0:1.2 [current_project]
34# Add the required static files.
35add_files $projDir/imports/xilinx_dma_pcie_ep.sv
36
37add_files $projDir/imports/xilinx_pcie_xdma_ref_board.xdc
38
39add_files $projDir/$projName.srcs/sources_1/ip/$ipName/xdma_0_board.xdc
40
41add_files $updateTopBlackboxFile
42# At this point the Out-of-Context IP module checkpoint can be used or the IP source can be used directly.
43if {[file exists $projDir/$projName.srcs/sources_1/ip/$ipName.xcix]} {
44 # Add the IP .xcix file if it exists.
45 add_files $projDir/$projName.srcs/sources_1/ip/$ipName.xcix
46 # Generate the IP .dcp file if required and it doesn't exist
47 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/$ipName.xcix]]} {
48 if {[get_files -quiet $projDir/$projName.srcs/sources_1/ip/$ipName/$ipName.dcp] == {}} {
49 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/$ipName.xcix] > $synthDir/$topModuleName/${ipName}_ooc_synth.log
50 }
51 }
52} else {
53 # Add the IP .xci file if the .xcix does not exist.
54 add_files $projDir/$projName.srcs/sources_1/ip/$ipName/$ipName.xci
55 # Generate the IP .dcp file if required and it doesn't exist
56 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/$ipName/$ipName.xci]]} {
57 if {![file exists $projDir/$projName.srcs/sources_1/ip/$ipName/$ipName.dcp]} {
58 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/$ipName/$ipName.xci] > $synthDir/$topModuleName/${ipName}_ooc_synth.log
59 }
60 }
61}
62
63# Downgrade DRC related to unconnected BSCAN ports. These are intentionally left uconnected.
64# Messages not related to these 12 BSCAN ports should be addressed appropriately
65set_msg_config -id {Synth 8-4442} -new_severity {Warning}
66
67# Run Synthesis on the static portion of the Tandem with Field Updates design and generate a post-synthesis checkpoint for the netlist.
68update_compile_order -fileset sources_1
69synth_design -flatten_hierarchy rebuilt -no_iobuf -top $topModuleName -part $part > $synthDir/$topModuleName/${topModuleName}_synth_design.log
70# Write the post_sysnthesis .dcp for use in later parts of the flow.
71write_checkpoint $synthDir/$topModuleName/${topModuleName}_synth.dcp
72
73# Error and Message Reporting
74set warningCount [get_msg_config -severity {Warning} -count]
75set criticalCount [get_msg_config -severity {Critical Warning} -count]
76set errorCount [get_msg_config -severity {Error} -count]
77puts "# HD INFO: Synthesis completed for Static with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
78set fp [open $runSummary a]
79puts $fp "Synthesis completed for Static with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
80close $fp
81
82# close the in-memory project.
83close_project
84return "$errorCount $criticalCount $warningCount"
update_ver1_impl.tcl
1
2# Setup of additional variables
3set updateName $updateVer1Name
4
5###############################################################################
6# This script runs implementation for a configuration of a Tandem with Field
7# Update design. This script is dependent on already having run synthesis for
8# the static design and this version of the update module. This script will
9# generate a place, routed, and LOC'ed static netlist used in implementation runs for subsequent field updates.
10# Note: This should be the most complex update design (if known) to improve the timing result of subsequent update runs.
11###############################################################################
12
13# Create the output directory and remove previously generated files.
14file mkdir $implDir
15file delete -force $implDir/$updateName
16file mkdir $implDir/$updateName
17
18puts "# HD INFO: Running implementation for configuration $updateName"
19
20# Create an in-memory project
21create_project -in_memory -part $part
22
23# Read in the synthesized static netlist
24add_files $synthDir/$topModuleName/${topModuleName}_synth.dcp
25link_design -mode default -part $part -top $topModuleName
26
27# Source any required .tcl files if they exist
28foreach tclFile $tclFiles {
29 if {[file exists $tclFile]} {
30 source $tclFile
31 }
32}
33
34# Read in this version of the update checkpoint and associated constraints.
35set_property HD.RECONFIGURABLE 1 [get_cells $updateInstName]
36read_checkpoint -cell $updateInstName $synthDir/$updateName/${updateModuleName}_synth.dcp -strict
37
38read_xdc $projDir/imports/xilinx_pcie_xdma_ref_board.xdc
39read_xdc $projDir/imports/${ipName}_tandem.xdc
40
41read_xdc $projDir/$projName.srcs/sources_1/ip/$ipName/xdma_0_board.xdc
42
43# Add additional properties that might be necessary
44
45# Write out a post link design checkpoint for this update of the Tandem with Field Update design.
46write_checkpoint -force $implDir/$updateName/${topModuleName}_link_design.dcp
47
48# Run the desired implementation steps. Additional implementation steps and
49# options can be added here as desired. A checkpoint is written after each step for convenience.
50opt_design > $implDir/$updateName/${topModuleName}_opt_design.log
51# Add the tool inserted dbg_hub instance to stage1 main pblock if it exists.
52if {[get_cells -quiet dbg_hub] != ""} {
53 set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells -quiet dbg_hub]
54}
55# Add the tool inserted dbg_hub clock buffer to stage1 config IO pblock if it exists.
56if {[get_cells -quiet -hierarchical -filter { PRIMITIVE_TYPE =~ CLOCK.*.* && NAME =~ "dbg_hub/*" }] != ""} {
57 set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells -quiet -hierarchical -filter { PRIMITIVE_TYPE =~ CLOCK.*.* && NAME =~ "dbg_hub/*" }]
58}
59# Add the tool inserted xvc_vsec clock buffer to stage1 config IO pblock if it exists.
60if {[get_cells -quiet -hierarchical -filter { PRIMITIVE_TYPE =~ CLOCK.*.* && NAME =~ "xdma_0_support_i/xvc_vsec_i/*" }] != ""} {
61 set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells -quiet -hierarchical -filter { PRIMITIVE_TYPE =~ CLOCK.*.* && NAME =~ "xdma_0_support_i/xvc_vsec_i/*" }]
62}
63write_checkpoint -force $implDir/$updateName/${topModuleName}_opt_design.dcp
64place_design > $implDir/$updateName/${topModuleName}_place_design.log
65write_checkpoint -force $implDir/$updateName/${topModuleName}_place_design.dcp
66route_design > $implDir/$updateName/${topModuleName}_route_design.log
67write_checkpoint -force $implDir/$updateName/${topModuleName}_route_design.dcp
68
69# Generate a timing report for convenience.
70report_timing_summary -warn_on_violation -file $implDir/$updateName/report_timing_summary.rpt
71
72# Generate a placed, routed, and LOC'ed update of the static netlist Blackbox the update module to remove it from the design.
73update_design -cell $updateInstName -black_box
74# Lock the placement and routing of the static portion of the design.
75lock_design -level routing
76# Generate a static checkpoint that will be used during the generation of all Update implementation runs.
77write_checkpoint -force $implDir/$updateName/${topModuleName}_static_routed.dcp
78
79# Error and Message Reporting
80set warningCount [get_msg_config -severity {Warning} -count]
81set criticalCount [get_msg_config -severity {Critical Warning} -count]
82set errorCount [get_msg_config -severity {Error} -count]
83puts "# HD INFO: Implementation for $updateName completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
84set fp [open $runSummary a]
85puts $fp "Implementation for $updateName completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
86close $fp
87
88# Close the in-memory project.
89close_project
90return "$errorCount $criticalCount $warningCount"
update_ver1_synth.tcl
1
2# Setup of additional variables
3set updateName $updateVer1Name
4
5###############################################################################
6# This script demonstrates how to synthesize the out-of-context, update module
7# that will be used for a Tandem with Field Updates design. This file is for
8# update version 1 which should be the most complex version of the design.
9###############################################################################
10
11# Create the output directory and delete the previously generated files.
12file mkdir $synthDir
13file delete -force $synthDir/$updateName
14file mkdir $synthDir/$updateName
15
16puts "# HD INFO: Running synthesis for module $updateName"
17
18# Create a synthesis project
19create_project -in_memory -part $part
20set_property BOARD_PART xilinx.com:kcu1500:part0:1.2 [current_project]
21# Add the required source files for this version of the update module.
22# This includes all files necessary for compiling this version of the update
23# module. This should be updated as desired for your application.
24add_files $projDir/imports/xdma_app.v
25# Add the blk_mem_gen_0 IP in the form it is found.
26if {[file exists $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix]} {
27 # Add the IP .xcix file if it exists.
28 add_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix
29 # Generate the IP .dcp file if required and it doesn't exist
30 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix]]} {
31 if {[get_files -quiet $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.dcp] == {}} {
32 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix] > $synthDir/$topModuleName/blk_mem_gen_0_ooc_synth.log
33 }
34 }
35} else {
36 # Add the IP .xci file if the .xcix does not exist.
37 add_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci
38 # Generate the IP .dcp file if required and it doesn't exist
39 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci]]} {
40 if {![file exists $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.dcp]} {
41 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci] > $synthDir/$topModuleName/blk_mem_gen_0_ooc_synth.log
42 }
43 }
44}
45
46
47# Add in the ILA core
48# Generate the IP if needed.
49if {[file exists $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix]} {
50 # Add the IP .xcix file if it exists.
51 add_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix
52 # Generate the IP .dcp file if required and it doesn't exist
53 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix]]} {
54 if {[get_files -quiet $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.dcp] == {}} {
55 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix] > $synthDir/$topModuleName/user_app_ila_ooc_synth.log
56 }
57 }
58} else {
59 # Add the IP .xci file if the .xcix does not exist.
60 add_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xci
61 # Generate the IP .dcp file if required and it doesn't exist
62 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xci]]} {
63 if {![file exists $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.dcp]} {
64 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xci] > $synthDir/$topModuleName/user_app_ila_ooc_synth.log
65 }
66 }
67}
68
69# Run out-of-context synthesis on this version of the update module.
70update_compile_order -fileset sources_1
71synth_design -mode out_of_context -flatten_hierarchy rebuilt -top $updateModuleName -part $part > $synthDir/$updateName/${updateModuleName}_synth_design.log
72# Create the synthesized checkpoint for this version of the update module.
73write_checkpoint -force $synthDir/$updateName/${updateModuleName}_synth.dcp
74
75# Error and Message Reporting
76set warningCount [get_msg_config -severity {Warning} -count]
77set criticalCount [get_msg_config -severity {Critical Warning} -count]
78set errorCount [get_msg_config -severity {Error} -count]
79puts "# HD INFO: Synthesis completed for $updateName with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
80set fp [open $runSummary a]
81puts $fp "Synthesis completed for $updateName with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
82close $fp
83
84# Close the in memory project that was created.
85close_project
86return "$errorCount $criticalCount $warningCount"
update_ver2_impl.tcl
1
2# Setup of additional variables
3set updateName $updateVer2Name
4
5###############################################################################
6# This script runs implementation for a configuration of a Tandem with Field
7# Update design. This script is dependent on already having run synthesis for
8# this version of the update module and having generated a place, routed, and
9# LOC'ed .dcp of the static netlist. This file must be replicated for
10# additional versions of the update module.
11###############################################################################
12
13# Create the output directory and remove previously generated files.
14file mkdir $implDir
15file delete -force $implDir/$updateName
16file mkdir $implDir/$updateName
17
18puts "# HD INFO: Running implementation for configuration $updateName"
19
20# Create an in-memory project
21create_project -in_memory -part $part
22
23# Read in the placed, routed, and LOC'ed static netlist
24add_files $implDir/$updateVer1Name/${topModuleName}_static_routed.dcp
25link_design -mode default -part $part -top $topModuleName
26
27# Source any required .tcl files if they exist
28foreach tclFile $tclFiles {
29 if {[file exists $tclFile]} {
30 source $tclFile
31 }
32}
33
34# Read in this version of update checkpoint and associated constraints.
35read_checkpoint -cell $updateInstName $synthDir/$updateName/${updateModuleName}_synth.dcp -strict
36read_xdc $projDir/imports/xilinx_pcie_xdma_ref_board.xdc
37read_xdc $projDir/imports/${ipName}_tandem.xdc
38
39read_xdc $projDir/$projName.srcs/sources_1/ip/$ipName/xdma_0_board.xdc
40
41
42# Add additional properties that might be necessary
43
44# Write out a post link design checkpoint for this update of the Tandem with Field Update design.
45write_checkpoint -force $implDir/$updateName/${topModuleName}_link_design.dcp
46
47# Run the desired implementation steps. Additional implementation steps and
48# options can be added here as desired. A checkpoint is written after each step for convenience.
49opt_design > $implDir/$updateName/${topModuleName}_opt_design.log
50write_checkpoint -force $implDir/$updateName/${topModuleName}_opt_design.dcp
51place_design > $implDir/$updateName/${topModuleName}_place_design.log
52write_checkpoint -force $implDir/$updateName/${topModuleName}_place_design.dcp
53route_design > $implDir/$updateName/${topModuleName}_route_design.log
54write_checkpoint -force $implDir/$updateName/${topModuleName}_route_design.dcp
55
56# Generate a timing report for convenience.
57report_timing_summary -warn_on_violation -file $implDir/$updateName/report_timing_summary.rpt
58
59# Error and Message Reporting
60set warningCount [get_msg_config -severity {Warning} -count]
61set criticalCount [get_msg_config -severity {Critical Warning} -count]
62set errorCount [get_msg_config -severity {Error} -count]
63puts "# HD INFO: Implementation for $updateName completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
64set fp [open $runSummary a]
65puts $fp "Implementation for $updateName completed with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
66close $fp
67
68# Close the in-memory project.
69close_project
70return "$errorCount $criticalCount $warningCount"
update_ver2_synth.tcl
1
2# Setup of additional variables
3set updateName $updateVer2Name
4
5###############################################################################
6# This script demonstrates how to synthesize the out-of-context, update module
7# that will be used for a Tandem with Field Updates design. This file should be
8# replicated for additional versions of the update module.
9###############################################################################
10
11# Create the output directory and delete the previously generated files.
12file mkdir $synthDir
13file delete -force $synthDir/$updateName
14file mkdir $synthDir/$updateName
15
16puts "# HD INFO: Running synthesis for module $updateName"
17
18# Create a synthesis project
19create_project -in_memory -part $part
20set_property BOARD_PART xilinx.com:kcu1500:part0:1.2 [current_project]
21# Add the required source files for this version of the update module.
22# This includes all files necessary for compiling this version of the update
23# module. This should be updated as desired for your application.
24add_files $projDir/imports/xdma_app.v
25# Add the blk_mem_gen_0 IP in the form it is found.
26if {[file exists $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix]} {
27 # Add the IP .xcix file if it exists.
28 add_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix
29 # Generate the IP .dcp file if required and it doesn't exist
30 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix]]} {
31 if {[get_files -quiet $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.dcp] == {}} {
32 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0.xcix] > $synthDir/$topModuleName/blk_mem_gen_0_ooc_synth.log
33 }
34 }
35} else {
36 # Add the IP .xci file if the .xcix does not exist.
37 add_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci
38 # Generate the IP .dcp file if required and it doesn't exist
39 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci]]} {
40 if {![file exists $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.dcp]} {
41 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.xci] > $synthDir/$topModuleName/blk_mem_gen_0_ooc_synth.log
42 }
43 }
44}
45
46
47# Add in the ILA core
48# Generate the IP if needed.
49if {[file exists $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix]} {
50 # Add the IP .xcix file if it exists.
51 add_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix
52 # Generate the IP .dcp file if required and it doesn't exist
53 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix]]} {
54 if {[get_files -quiet $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.dcp] == {}} {
55 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xcix] > $synthDir/$topModuleName/user_app_ila_ooc_synth.log
56 }
57 }
58} else {
59 # Add the IP .xci file if the .xcix does not exist.
60 add_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xci
61 # Generate the IP .dcp file if required and it doesn't exist
62 if {[get_property generate_synth_checkpoint [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xci]]} {
63 if {![file exists $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.dcp]} {
64 synth_ip [get_files $projDir/$projName.srcs/sources_1/ip/user_app_ila/user_app_ila.xci] > $synthDir/$topModuleName/user_app_ila_ooc_synth.log
65 }
66 }
67}
68
69# Run out-of-context synthesis on this version of the update module.
70update_compile_order -fileset sources_1
71synth_design -mode out_of_context -flatten_hierarchy rebuilt -top $updateModuleName -part $part > $synthDir/$updateName/${updateModuleName}_synth_design.log
72# Create the synthesized checkpoint for this version of the update module.
73write_checkpoint -force $synthDir/$updateName/${updateModuleName}_synth.dcp
74
75# Error and Message Reporting
76set warningCount [get_msg_config -severity {Warning} -count]
77set criticalCount [get_msg_config -severity {Critical Warning} -count]
78set errorCount [get_msg_config -severity {Error} -count]
79puts "# HD INFO: Synthesis completed for $updateName with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings.\n"
80set fp [open $runSummary a]
81puts $fp "Synthesis completed for $updateName with $errorCount Errors, $criticalCount Critical Warnings, and $warningCount Warnings at [clock format [clock seconds]]."
82close $fp
83
84# Close the in memory project that was created.
85close_project
86return "$errorCount $criticalCount $warningCount"
xdma_0_tandem.xdc
1
2###############################################################################
3# Enable Tandem PCIE Bitstream Generation
4###############################################################################
5# Uncomment the following two constraints to generate Tandem PCIe Bitstreams.
6# Without these constraints Tandem PROM bitstreams will be generated.
7#set_property HD.OVERRIDE_PERSIST FALSE [current_design]
8#set_property HD.TANDEM_BITSTREAMS Separate [current_design]
9
10###############################################################################
11# Tandem Pblocks for the Example Design:
12# All Stage1 primitives must be in a PBlock that is aligned to a Programmable
13# Unit boundary. This PBlock must have exclude placement to prevent other
14# primitives from being included in the region boundary.
15###############################################################################
16
17## Since the reset pin is within the config IO Bank, add the Reset IOB to the
18## config IO Bank pblock that is already created by the solution IP
19set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells sys_reset_n_ibuf]
20
21## If the reset pin is NOT in the config bank the reset pin IOB must also have a pblock
22## The following commands might be helpful in achiving this. For US devices you must
23## disable dedicated PCIe reset routing to move the reset pin to a new location.
24## Create the PBlock for the IO bank containing the system reset pin
25#set stage1Pblock [create_pblock resetPblock]
26## Resize the PBlock for the IO bank containing the system reset pin
27#resize_pblock $stage1Pblock -add {IOB_X2Y52:IOB_X2Y103 \
28# SLICE_X96Y60:SLICE_X96Y119 \
29# MMCME3_ADV_X2Y1 \
30# PLLE3_ADV_X2Y2:PLLE3_ADV_X2Y3 \
31# PLL_SELECT_SITE_X2Y8:PLL_SELECT_SITE_X2Y15 \
32# BITSLICE_CONTROL_X2Y8:BITSLICE_CONTROL_X2Y15 \
33# BITSLICE_TX_X2Y8:BITSLICE_TX_X2Y15 \
34# BITSLICE_RX_TX_X2Y52:BITSLICE_RX_TX_X2Y103 \
35# XIPHY_FEEDTHROUGH_X8Y1:XIPHY_FEEDTHROUGH_X11Y1 \
36# RIU_OR_X2Y4:RIU_OR_X2Y7 \
37#}
38## Map the reset IOB to the reset_iob pblock using the Stage1_IO tag.
39#set_property HD.TANDEM_IP_PBLOCK Stage1_IO $stage1Pblock
40#set_property HD.TANDEM_IP_PBLOCK Stage1_IO [get_cells sys_reset_n_ibuf]
41
42# Since the LEDs are within the stage1 config IO Bank, add the LED IOBs to the
43# config IO Bank pblock that is already created by the solution IP and mark them as stage1.
44# set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells {led_0_obuf led_1_obuf led_2_obuf led_3_obuf}]
45
46
47# Since the refclk is within the range of the main pblock, add the refclk IBUF and its BUFG_GT to the main pblock.
48set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells refclk_ibuf]
49
50###############################################################################
51# The following constraints can be used to demonstrate Tandem with
52# Field-Updates. For this example the user_application will be setup
53# for field updates. The required steps are below to enable this.
54###############################################################################
55## Store the sites for existing stage1 pblocks so that they can be removed from the Update Region Pblock.
56set existingStage1Sites [get_sites -of_objects [get_pblocks -filter { \
57 NAME =~ *_xdma_0_pcie3_ip_Stage1_main || \
58 NAME =~ *_Stage1_cfgiob \
59}]]
60
61#####################################################################################################
62## Set the module as reconfigurable
63set_property HD.RECONFIGURABLE 1 [get_cells xdma_app_i]
64## Create the Update Region PBlock
65set updatePblock [create_pblock -quiet update_region]
66## Add the Update Region module to the Update Region pblock
67## Note: One and only one module/cell can be added to this pblock
68add_cells_to_pblock -quiet $updatePblock [get_cells xdma_app_i]
69## Resize the Update Region PBlock to include all available programmable units
70resize_pblock -quiet $updatePblock -add {SLICE_X0Y0:SLICE_X142Y599 \
71 DSP48E2_X0Y0:DSP48E2_X22Y239 \
72 RAMB18_X0Y0:RAMB18_X17Y239 \
73 RAMB36_X0Y0:RAMB36_X17Y119 \
74 GTHE3_CHANNEL_X0Y8:GTHE3_CHANNEL_X0Y39 GTHE3_CHANNEL_X1Y0:GTHE3_CHANNEL_X1Y39 \
75 GTHE3_COMMON_X0Y2:GTHE3_COMMON_X0Y9 GTHE3_COMMON_X1Y0:GTHE3_COMMON_X1Y9 \
76 PCIE_3_1_X0Y0:PCIE_3_1_X0Y5 \
77 MMCME3_ADV_X0Y0:MMCME3_ADV_X2Y9 \
78 PLLE3_ADV_X0Y0:PLLE3_ADV_X2Y19 \
79 RIU_OR_X0Y0:RIU_OR_X2Y39 \
80 PLL_SELECT_SITE_X0Y0:PLL_SELECT_SITE_X2Y79 \
81 BITSLICE_CONTROL_X0Y0:BITSLICE_CONTROL_X2Y79 \
82 BITSLICE_TX_X0Y0:BITSLICE_TX_X2Y79 \
83 BITSLICE_RX_TX_X0Y0:BITSLICE_RX_TX_X2Y519 \
84 IOB_X0Y0:IOB_X2Y519 \
85 XIPHY_FEEDTHROUGH_X0Y0:XIPHY_FEEDTHROUGH_X11Y9 \
86 SYSMONE1_X0Y0:SYSMONE1_X0Y1 \
87 LAGUNA_X0Y120:LAGUNA_X23Y479 \
88}
89## Resize the Update Region PBlock to remove sites adjacent to the config sites
90resize_pblock -quiet $updatePblock -remove {SLICE_X129Y360:SLICE_X130Y419}
91## Remove Config site programmable units from the update region. These are not reconfigurable.
92resize_pblock $updatePblock -remove [get_sites -of_objects [get_tiles -pu -of_objects [get_tiles -of_objects [get_sites -filter {SITE_TYPE == "CONFIG_SITE"}]]]]
93## Resize the Update PBlock to remove sites already associated with Stage1
94resize_pblock -quiet $updatePblock -remove $existingStage1Sites
95## Resize the Update PBlock to remove sites for the XDMA logic. this logic will
96## be part of stage2 for the initial configuration, but will NOT be reconfigured during an "Update".
97resize_pblock -quiet $updatePblock -remove "SLICE_X97Y0:SLICE_X125Y149 SLICE_X126Y60:SLICE_X128Y149 \
98 DSP48E2_X18Y0:DSP48E2_X22Y59 \
99 RAMB18_X12Y0:RAMB18_X15Y59 RAMB18_X16Y24:RAMB18_X16Y59 \
100 RAMB36_X12Y0:RAMB36_X15Y29 RAMB36_X16Y12:RAMB36_X16Y29 \
101"
102
103## Increase the partition pin density near the PCIe core. This is done to improve timing
104## accross the PR boundary. If the design is unable to partition pin and/or routing
105## congestion, this number should be decreased.
106#set_property PARTPIN_SPREADING 8 [get_pblocks update_region]
107
108## Set the Part Pin Range to improve the placement of the RM Partition Pins.
109set_property HD.PARTPIN_RANGE -quiet {SLICE_X80Y0:SLICE_X96Y59 SLICE_X80Y60:SLICE_X95Y119 SLICE_X80Y120:SLICE_X96Y149} [get_pins -of_objects [get_cells xdma_app_i]]
110
111## Set a location constraint on logic directly connected to the partition pins. This will
112## aid the placer to ensure the connected logic is placed next to the partition pins and
113## improve timing.
114set stage2LogicPblock [create_pblock pcie_interface_logic]
115resize_pblock -quiet $stage2LogicPblock -add {SLICE_X80Y0:SLICE_X96Y59 SLICE_X80Y60:SLICE_X95Y119 SLICE_X80Y120:SLICE_X96Y149 \
116 DSP48E2_X15Y0:DSP48E2_X17Y59 \
117 RAMB18_X10Y0:RAMB18_X11Y59 \
118 RAMB36_X10Y0:RAMB36_X11Y29 \
119}
120## This constraint will need to be modified for your application and desired
121## connectivity and design
122add_cells_to_pblock $stage2LogicPblock [get_cells -hierarchical -filter { \
123 PARENT == xdma_app_i && \
124 ( !IS_PRIMITIVE || \
125 ( IS_PRIMITIVE && \
126 PRIMITIVE_LEVEL != INTERNAL && \
127 PRIMITIVE_TYPE != OTHERS.others.GND && \
128 PRIMITIVE_TYPE != OTHERS.others.VCC ))}]
xilinx_pcie_xdma_ref_board.xdc
1
2#########################################################################################################################
3# User Constraints
4#########################################################################################################################
5###############################################################################
6# User Time Names / User Time Groups / Time Specs
7###############################################################################
8create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]
9set_false_path -from [get_ports sys_rst_n]
10#set_false_path -through [get_pins xdma_0_i/inst/pcie3_ip_i/inst/xdma_0_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/CFGMAX*]
11#set_false_path -through [get_nets xdma_0_i/inst/cfg_max*]
12
13###############################################################################
14# User Physical Constraints
15###############################################################################
16###############################################################################
17# Pinout and Related I/O Constraints
18###############################################################################
19
20
21#set_property LOC [get_package_pins -filter {PIN_FUNC == IO_T3U_N12_PERSTN0_65}] [get_ports sys_rst_n]
22set_property PACKAGE_PIN AR26 [get_ports sys_rst_n]
23set_property PULLUP true [get_ports sys_rst_n]
24set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n]
25
26set_property CONFIG_VOLTAGE 1.8 [current_design]
27set_property CFGBVS GND [current_design]
28
29##### REFCLK_IBUF###########
30#set_property LOC GTHE3_COMMON_X1Y1 [get_cells refclk_ibuf]
31set_property LOC AT11 [get_ports sys_clk_p]
32##### LED's ###########
33set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
34######################################################################
35#
36set_false_path -to [get_pins -hier *sync_reg[0]/D]
37#
