Annotation
Useful aggregator from LinkedIn/Twitter/WikiChip/SemiWiki/etc linked with FPG/A/SIC for work/hobby topics here.
In terms of community initiative made a couple of telegram channels with FPG/A/SIC related topics, mainly with useful tips and tricks, interesting opensource projects and similar things. Please find details below.
IP-cores
Verilog/VHDL-written collection of IP-cores for ASIC/FPGA usage. Most of IP cores are opensource that allow to free use in own project. Besides peripheral and interface IP cores collection contain CPU cores (MIPSopen, RISC-V, etc) and also contain primitives library (FIFO, CDC things, others parametric primitives) and algorithms library (signal processing primitives, error detection/correction, CRC/ECC, etc).
Which IP-related topics already covered?
- DisplayPort, HDMI, DVI, VGA
- HMC (Hybrid Memory Cube)
- DDR3 controller
- PCI-E + DMA engine
- Interconnect core, NoC
- Bridges to FX2LP (CY7C68013), FX3, FT2232
- AXI buses (itself + Bus Functional Model + Assertions)
- PonyLink
- HyperBUS
- USB2 (ULPI)
- USB3 (PIPE),
- RNG, TRNG
- Cryptography cores: hashes, stream ciphers, assymetric ciphers
- MIPI DSI, MIPI CSI
- HyperRAM
- will be continue…
The channel has a convenient tag search.
Link
FPG[A]SIC
The main topic for this channel - Design Automation, i.e. rejection to work in GUI in favor CLI-approach for routine automation.
Besides you can find on channel useful info with following topics:
- Tips for EDA-tools (Cadence/Synopsys, Vivado, Quartus, Yosys, ICEstorm, Verilator, Icarus Verilog, etc)
- Design Automation script examples
- HDL tips and tricks
- Tricks for useful/unobvious tcl-command
- Undocumented/out-of-the-way tools power
- OpenSource HLS (High level synthesis) tools
- NN/ML-frameworks (Neural Network and Machine Learning) targeted to FPGA
- Scripts for auto building datasheets
- Approaches for usage free and OSS tools for formal verification
- HDL plugins and addons for text editors and IDE
- Free book related to FPGA and HDL topics
- Advice to LINT tool tuning
- Nuance of FPG/A/SIC project versioning in git
- Tips and tricks for timing closure (e.g. best fragments of Ultrafast Methodology)
- Clock conversion and constraining (SDC, XDC)
- References to FPGA bitstream and architecture reverse engineering
- Free translator anything to HDL (e.g. Python -> Verilog as most popular)
- Advanced approaches for BRAM/DSP folding/multi-pumping
- Hierarchical design approach, Partitions and Partial Reconfiguration (PR)
- Example of usage DNA design protection, etc.
The channel has a convenient tag search.