Common Cells

• Inferring true dual-port, dual-clock RAMs in Xilinx and Altera FPGAs

• https://github.com/bespoke-silicon-group/basejump_stl

• https://github.com/ultraembedded/cores

• https://github.com/pulp-platform/common_cells

• https://github.com/Wren6991/libfpga

• https://github.com/pConst/basic_verilog Must-have verilog systemverilog modules

• https://github.com/Luke7412/IpLibrary Library containing various SV/VHDL IPs

• https://github.com/pezy-computing/pzbcm Basic Common Modules

CDC (clock domain crossing)

• https://github.com/hdl-util/clock-domain-crossing
• https://github.com/pulp-platform/apb_asynch_cdc

VHDL

• https://github.com/slaclab/surf

Peripherals

• https://github.com/FPGAwars/FPGA-peripherals

Frameworks/API

• SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.
• https://github.com/taichi-ishitani/tue Useful UVM extensions